1. Field of the Invention
The present invention relates to an embedded semiconductor device and a system and method for fabricating an embedded semiconductor device, and in particular to a system and method for fabricating an embedded semiconductor device having a logic device and a memory device embedded into a single chip.
2. Description of the Background Art
Conventionally, semiconductor devices having singular functions are independently fabricated and mounted on a system board, and those devices are then connected with each other to implement a predetermined system. As the fabrication technology of the semiconductor device is advanced and a high performance of the system is required, a system-on-a-chip method and an embedded semiconductor device fabrication method have been used. In the system-on-a-chip method, a plurality of semiconductor devices that perform a single function are mounted onto one chip.
One known embedded semiconductor device fabrication method is typically used to embed a DRAM (Dynamic Random Access Memory) and a microprocessor into one chip. However, any one of several different fabrication processes may be used to fabricate the above-described embedded semiconductor devices, so that the fabrication thereof is complicated. Therefore, it is important to simplify the fabrication processes for fabricating various functional devices.
A known semiconductor device into which a DRAM cell and a logic device are embedded, and a fabrication method thereof will now be explained with reference to the accompanying drawings.
In FIG. 1, relative to the broken-line, the DRAM cell is illustrated in the left portion, and the logic devices are illustrated in the right portion. The left portion in the drawing is called a first region "a" and the right portion in the drawing illustrating the logic device is called a second region "b".
A plurality of device isolation regions 2 and a plurality of active regions 3 are formed in the semiconductor substrate 1 of the first region "a" and the second region "b". A gate insulation film 4 is formed on the active regions 3 of the first region "a" and the second region "b". In addition, a gate electrode 5 formed of a first conductive film pattern 5a and a second conductive film pattern 5b is formed on the gate insulation film 4. The first conductive film pattern 5a is formed of a polysilicon layer, and the second conductive film pattern 5b is formed of a metallic layer or a silicide layer. A side wall spacer 7 formed of an insulation film is formed on a lateral surface of the gate electrode 5, and source and drain electrodes 8a and 8b are formed on the surface of the semiconductor substrate and at both sides of the side wall spacer 7. In the drawings, reference numeral 8a denotes a source/drain formed in the first region, and 8b denotes a source/drain formed in the second region. The above-described construction is a common structure of the devices formed in the first region "a" and the second region "b".
Additional features of the devices formed in the second region "b" will now be explained in greater detail. A third conductive film pattern 10 is formed on the surface of the source/drain 8b. The third conductive film pattern 10 is a metallic layer or a silicide layer. Namely, in the logic device, the silicide layer 10 is formed on the surface of the source/drain 8b for decreasing the resistance of the source/drain 8b and reducing the occupying area of the chips. However, in the case of the DRAM cell mounted in the first region "a", when the silicide layer is formed on the surface of the source/drain 8a, since a junction current leakage problem may occur, the silicide layer is not formed thereon.
The known fabrication method for a semiconductor device, as shown in FIG. 1, will now be explained with reference to FIGS. 2A-2C. In the process of FIG. 2A, a plurality of device isolation regions 2 are formed in the semiconductor substrate 1 using a LOCOS process or a method for filling an oxide film into a trench after forming the trench. An active region 3 is formed on a surface of the semiconductor substrate, except the portions of the substrate corresponding to device region 2, by slightly doping an impurity. A gate insulation film 4 is formed on the front surface of the semiconductor substrate. A polysilicon layer for forming a first conductive film and a silicide layer for forming a second conductive film or a metallic layer are deposited on the gate insulation film 4. A protection film is deposited on the metallic layer. The protection film includes a side wall spacer which will be used later and a member that has a high etching selectivity, for example, an oxide film, a nitride film, a PSG (phosphorous silicate glass, etc.). The protection film, the second conductive film, and the first conductive film are selectively etched to form the protection film pattern 6a, the second conductive film pattern 5b the first conductive film pattern 5a shown in FIG. 2A The second conductive film pattern 5b and the first conductive film pattern 5a together form a gate electrode 5. The protection film pattern 6a is used to limit the height of the gate electrode 5 when the second conductive film pattern 5b of the gate electrode 5 reacts with a silicide during the self-aligning process shown in FIG. 2B, which involves self-forming the silicide on the surface of the source/drain within the second region "b".
An insulation film is formed on the entire structure of the semiconductor substrate 1 and then is etched-back to form a side wall spacer 7 on a lateral surfaces of the gate electrode 5. A predetermined dopant is implanted into the surface of the semiconductor substrate 1 using the protection film pattern 6a and the side wall spacer 7 as a mask, thereby forming the source/drain electrodes 8a and 8b.
As shown in FIG. 2B, a mask pattern 9 is formed on the entire structure of the semiconductor substrate 1 of the first region "a" using a photo resist.
Next, a metallic layer such as titanium, nitride titanium or tungsten is formed on the resultant entire structure that has been formed on the semiconductor substrate 1 of the second region, and a silicidation reaction occurs between the metallic layer and the source/drain 8b by heat-treating the resultant structure. In the source/drain 8b, the silicon component of the semiconductor substrate 1 and the metallic component of the metallic layer are engaged to perform the silicidation reaction. As a result, the silicidation reaction is not performed with respect the metallic layer formed on the side wall spacer 7 and the protection film pattern 6a. The portions of the metallic layer not involved in the silicidation reaction is selectively removed by a wet etching operation using NH.sub.3 or H.sub.2 O.sub.2. Thus, a silicide layer, hereinafter known as the third conductive film pattern 10, is formed only on the surface of the source/drain 8 of the devices mounted in the second region "b" as shown in FIG. 2b.
Thereafter, as shown in FIG. 3C, the mask pattern 9 is removed, so that the fabrication of the known embedded semiconductor device is finished.
In the known semiconductor device fabrication process, even though the second conductive film pattern and the third conductive film pattern are made of the same material, a step for forming the third conductive film pattern on the surface of the source/drain is additionally performed after forming the second conductive film pattern as an upper layer of the gate electrode. Therefore, the fabrication process is complicated, decreasing productivity.
In addition, when using the metallic film rather than a silicide film as the upper layer 5b of the gate electrode, there must be a height limit imposed upon the gate electrode. Due to this height limitation, the height of the polysilicon layer forming the lower layer of the gate electrode is effectively decreased. When the height of the polysilicon layer becomes lower than 1000 A, it is difficult to perform a polysilicon layer doping operation for adjusting the threshold voltage Vth. Namely, in the known art, after the polysilicon layer is doped, the dopant of the polysilicon may penetrate into the gate insulation film formed below the gate electrode or the surface of the semiconductor substrate during the heat treatment process, so that the characteristic of the semiconductor device may be decreased.